Several types of memory devices, such as Flash memories and Dynamic Random Access Memory (DRAM), use arrays of analog memory cells for storing data. Flash memory devices are described, for example, by Bez et al., in “Introduction to Flash Memory,” Proceedings of the IEEE 91:4 (April, 2003), pages 489-502, which is incorporated herein by reference. In such memory devices, each analog memory cell typically comprises a transistor, which holds a certain amount of electric charge that represents the information stored in the cell. The electric charge written into a particular cell influences the “threshold voltage” of the cell, i.e., the voltage that needs to be applied to the cell so that the cell will conduct current.
Some memory devices, commonly referred to as Single-Level Cell (SLC) devices, store a single bit of information in each memory cell. Typically, the range of possible threshold voltages of the cell is divided into two regions. A voltage value falling in one of the regions represents a “0” bit value, and a voltage belonging to the second region represents “1”. Higher-density devices, often referred to as Multi-Level Cell (MLC) devices, store more than one bit per memory cell. In multi-level cells, the range of threshold voltages is divided into more than two regions, with each region representing more than one bit.
Multi-level Flash cells and devices are described, for example, by Eitan et al., in “Multilevel Flash Cells and their Trade-Offs,” Proceedings of the 1996 IEEE International Electron Devices Meeting (IEDM) (New York, N.Y.), pages 169-172, which is incorporated herein by reference. The paper compares several kinds of multilevel Flash cells, such as common ground, DINOR, AND, NOR and NAND cells. Other types of analog memory cells that are known in the art include Nitride Read Only Memory (NROM), Ferroelectric RAM (FRAM), Magnetic RAM (MRAM) and Phase change RAM (PRAM, also referred to as Phase Change Memory—PCM).
In some applications, the data stored in the memory device is encoded using an Error Correcting Code (ECC). For example, Rodney and Sayano describe a number of on-chip coding techniques for the protection of Random Access Memory (RAM) devices, which use multi-level storage cells, in “On-Chip ECC for Multi-Level Random Access Memories,” Proceedings of the 1989 IEEE/CAM Information Theory Workshop (Jun. 25-29, 1989, Ithaca, N.Y.), which is incorporated herein by reference. As another example, U.S. Pat. No. 6,212,654, whose disclosure is incorporated herein by reference, describes methods for storing data in an analog memory device using coded modulation techniques. Other ECC schemes for multilevel memory devices are described in U.S. Pat. Nos. 6,469,931 and 7,023,735, whose disclosures are incorporated herein by reference.
The threshold voltage values read from analog memory cells are sometimes distorted. The distortion may be due to various causes, such as electrical field coupling from neighboring memory cells, disturb noise caused by operations on other cells in the array, and threshold voltage drift caused by device aging. Some common distortion mechanisms are described in the article by Bez et al., cited above.
U.S. Pat. No. 5,867,429, whose disclosure is incorporated herein by reference, describes a method for compensating for electric field coupling between floating gates of a high-density Flash Electrically Erasable Programmable Read Only Memory (EEPROM) cell array. A reading of a cell is compensated by first reading the states of all cells that are field-coupled with the cell being read. A number related to either the floating gate voltage or the state of each coupled cell is then multiplied by the coupling ratio between the cells. The breakpoint levels between states for each of the cells are adjusted by an amount that compensates for the voltage coupled from adjacent cells.